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commander
lemmy.world
commander@lemmy.world Joined: 2024-12-02 |
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Rekall Incorporated
Moderator
Rekall_Incorporated@piefed.socialJoined: 2025-06-08 |
Some background on the performance claims from The Register :
M1 level performance (I am curious if it matches the M1 on efficiency) is not bad for RISC-V. |
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Treczoks
lemmy.world
Treczoks@lemmy.world Joined: 2023-07-09 |
"Highest performing RISC-V" does not mean a lot. Most contemporary ARM cores will run circles around this chip. |
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beeng
discuss.tchncs.de
beeng@discuss.tchncs.de Joined: 2023-07-23 |
"Highest performing RISC-V" does not mean a lot. Most contemporary ARM cores will run circles around this chip.
Fair, but atleast they do didn't have to pay anybody for the "license" to use it. Other commenter is mentioning M1 performance.. Not bad. |
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Treczoks
lemmy.world
Treczoks@lemmy.world Joined: 2023-07-09 |
Fair, but atleast they do didn't have to pay anybody for the "license" to use it. Other commenter is mentioning M1 performance.. Not bad.
Well, it is either pay a license fee for a mature and fast design, or use a free design that still has to catch up performancewise. Both have their uses. |
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